With the gradual decrease of the critical size of semiconductor devices, various micro effects begin to occur, and it is becoming more difficult to optimize the performance of the semiconductor device, wherein the research for reducing the contact resistance of the contact hole of the source/drain (S/D) region is very challenging and practically significant.
As illustrated in FIG. 1, an S/D region 40 may be made of semiconductor material. The S/D region 40 is located at both sides of a gate stack structure (the gate stack structure includes a gate dielectric layer 12 formed on a substrate 10, a gate 14 formed on the gate dielectric layer 12, and sidewall spacers 16 surrounding the gate dielectric layer 12 and the gate 14) and embedded into the substrate 10. The difference between an actual height and a target height of the S/D region 40 is less than an error standard. In order to reduce the contact resistance, when a contact hole 30 abutting the S/D region 40 is formed in an interlayer dielectric layer 20, a contact region 18 (e.g., metal silicide) shall be formed on the surface of the S/D region 40 after the contact hole 30 is formed, so that the contact hole 30 abuts the S/D region 40 via the contact region 18. Thus, the key for the reduction of the contact resistance is to reduce a resistance of the contact region 18.
In order to reduce the resistance of the contact region, theoretically, a technical solution increasing the area of the contact region may be adopted. However, with the gradual decrease of the critical size of semiconductor devices, the critical size of the contact hole also gradually decreases, and it becomes a major problem urgently to be solved by a person skilled in the art to increase the area of the contact region in practice.